Computer and Modernization ›› 2012, Vol. 1 ›› Issue (11): 145-148+.doi: 10.3969/j.issn.1006-2475.2012.11.036
• 信息安全 • Previous Articles Next Articles
YIN Wei-feng
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Abstract: This paper presents a compact hardware architecture for the AES algorithm which aims at reducing hardware resources without using a memory. The architecture only requires one combined S-box for encryption, decryption and key expansion which implements the multiplicative inverse in the composite field GF(24). In addition, the optimized combined MixColumns module has a lower gate count than other designs that implement mix columns operation. VHDL code is developed for the implementation of 128-bit data encryption with Device Cyclone of Altera Family.
Key words: symmetric block cipher, Rijndael algorithm, advanced encryption standard, Gauss field
CLC Number:
TP309
TP368.1
YIN Wei-feng. Resource Optimization of Advanced Encryption Standard and Its Implementation for FPGA[J]. Computer and Modernization, 2012, 1(11): 145-148+.
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URL: http://www.c-a-m.org.cn/EN/10.3969/j.issn.1006-2475.2012.11.036
http://www.c-a-m.org.cn/EN/Y2012/V1/I11/145